Increased miniaturization of components, greater packaging density of integrated circuits (“ICs”), higher performance, and lower cost are ongoing goals of the computer industry. As new generations of IC products are released, the number of devices used to fabricate them tends to decrease due to advances in technology. Simultaneously, the functionality of these products increases. For example, on average there is approximately a 10 percent decrease in components for every product generation over the previous generation with equivalent functionality.
Semiconductor package structures continue to advance toward miniaturization and thinning to increase the density of the components that are packaged therein while decreasing the sizes of the products that are made therefrom. This is in response to continually increasing demands on information and communication apparatus for ever-reduced sizes, thicknesses, and costs, along with ever-increasing performance.
These increasing requirements for miniaturization are particularly noteworthy, for example, in portable information and communication devices such as cellular phones, hands-free cellular phone headsets, personal data assistants (“PDA's”), camcorders, notebook personal computers, and so forth. All of these devices continue to be made smaller and thinner to improve their portability. Accordingly, large scale IC (“LSI”) packages that are incorporated into these devices are required to be made smaller and thinner, and the package configurations that house and protect them are required to be made smaller and thinner as well.
Many conventional semiconductor die (or “chip”) packages are of the type where a semiconductor die is molded into a package with a resin, such as an epoxy molding compound. The packages have a lead frame whose out leads are projected from the package body, to provide a path for signal transfer between the die and external devices. Other conventional package configurations have contact terminals or pads formed directly on the surface of the package.
Such a conventional semiconductor package is fabricated through the following processes: a die-bonding process (mounting the semiconductor die onto the paddle of a lead frame), a wire-bonding process (electrically connecting the semiconductor die on the paddle to inner leads using lead frame wires), a molding process (encapsulating a predetermined portion of the assembly, containing the die, inner leads and lead frame wires, with an epoxy resin to form a package body), and a trimming process (completing each assembly as individual, independent packages).
The semiconductor packages, thus manufactured, are then mounted by matching and soldering the external leads or contact pads thereof to a matching pattern on a circuit board, to thereby enable power and signal input/output (“I/O”) operations between the semiconductor devices in the packages and the circuit board.
An exemplary semiconductor package, well known in the electronics industry, is the ball-grid array (“BGA”). BGA packages typically comprise a substrate, such as a printed circuit board (“PCB”), with a semiconductor die having a multitude of bond pads mounted to the top side of the substrate. Wire bonds electrically connect the bond pads to a series of metal traces on the top side of the PCB. This series of metal traces is connected to a second series of metal traces on the back side of the PCB through a series of vias located around the outer periphery of the PCB. The second series of metal traces each terminates with a contact pad where a conductive solder ball is attached. Typically, the semiconductor die and the wire bonds are encapsulated within a molding compound.
In order to reduce manufacturing costs, the electronics industry is increasing the usage of perimeter BGA packages. In perimeter BGA packages, the conductive solder balls are arranged in an array pattern on the back side of the PCB between the vias and the semiconductor die. The inner-most conductive solder balls typically are beneath or in close proximity to the outer edges of the semiconductor die.
Still thinner, smaller, and lighter package designs and mounting/connecting configurations have been adopted in response to continuing requirements for further miniaturization. At the same time, users are demanding semiconductor packages that are more reliable under increasingly severe operating conditions.
Thus, a need still remains for a stackable multi-chip package system providing low cost manufacturing, increased miniaturization, greater packaging densities, improved yield, and improved reliability that are capable of achieving optimal thin, high-density footprint. In view of the ever-increasing need to save costs and improve efficiencies, it is more and more critical that answers be found to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.